Re-exports§
pub use registers::IntRegisters;pub use earlycon::*;
Modules§
- boot
- context
- Kernel context switching for RISC-V 64-bit
- earlycon
- Early console driver for RISC-V64 architecture.
- fdt
- fpu
- Floating-Point Unit and Vector context for RISC-V 64-bit
- instruction
- interrupt
- RISC-V specific interrupt control functions
- kernel
- mmio
- MMIO access helpers for RISC-V.
- registers
- RISC-V 64-bit register module.
- switch
- RISC-V kernel context switching implementation
- timer
- trap
- vcpu
- VCPU module for RISC-V 64-bit architecture.
- vm
- Virtual memory module for RISC-V architecture.
Structs§
Constants§
- NO_
VECTOR_ 🔒OWNER - Per-hart ownership of the live Vector register file.
Statics§
- CPUS 🔒
- VECTOR_
OWNER 🔒 - VECTOR_
OWNER_ 🔒DIRTY - Whether the live vector register file contains state that is newer than the
saved per-task context of
VECTOR_OWNER.
Functions§
- configure_
user_ entry - Apply user-entry options for the upcoming
sret. - disable_
interrupt - enable_
interrupt - first_
switch_ to_ user - RISC-V: perform the very first transition into a runnable user task.
- get_cpu
- get_
device_ memory_ areas - Returns the device memory areas for RISC-V QEMU virt platform. These areas contain memory-mapped I/O devices and should be mapped with device memory attributes (non-cacheable, no speculation).
- get_
kernel_ trap_ handler - get_
kernel_ trapvector_ paddr - get_
user_ trap_ handler - get_
user_ trapvector_ paddr - get_
vector_ 🔒owner - get_
vector_ 🔒owner_ dirty - io_mb
- Full barrier for device/MMIO (I/O) operations.
- io_rmb
- Read barrier for device/MMIO (I/O) operations.
- io_wmb
- Write barrier for device/MMIO (I/O) operations.
- mb
- Full memory barrier for normal memory (RAM).
- mmio_
fence - Backward-compatible alias for a full device/MMIO barrier.
- reboot
- rmb
- Read memory barrier for normal memory (RAM).
- set_
arch - set_
next_ mode - set_
trapvector - set_
vector_ 🔒owner - set_
vector_ 🔒owner_ dirty - shutdown
- shutdown_
with_ code - trap_
init 🔒 - wmb
- Write memory barrier for normal memory (RAM).